A conventional binary logic based digital system has focused on increasing the bit density through miniaturization of CMOS device so as to quickly process a large amount of data. However, due to recent integration of sub-30 nm structures, there has been a limitation in increasing the bit density due to a leakage current and an increase in power consumption caused by a quantum tunneling effect. In order to overcome such limitation regarding the bit density, ternary logic devices and circuits have attracted much attention. In particular, most efficient ternary logic and its basic unit, standard ternary inverter (STI), has been actively developed. However, unlike a conventional binary inverter that uses a single CMOS with a single power source, conventional techniques for an STI require more power sources or complicated circuit configurations.